Hi Kevin,
would it be possible to send me the circuit of your voltage-regulator?
Because, we build an own regulator with Vout of 13V.
But it behaves not intented.
Below 10V it delivers 6V and above 10V it shuts down.
Thank you very much
Fabian
Hi Kevin,
would it be possible to send me the circuit of your voltage-regulator?
Because, we build an own regulator with Vout of 13V.
But it behaves not intented.
Below 10V it delivers 6V and above 10V it shuts down.
Thank you very much
Fabian
Hello,
for a study project, me and a fellow student created a circuit to convert a wide range input voltage to 13V.
These 13V are to charge a batterypack.
The voltageregulation circuit is based on the buck/boost IC LM25118.
Our problem ist, that the circuit does not behave like intented.
> Below 10V input voltage it converts it into ~6V and below 10V it shuts down.
What ever the problem is, we assume the problem is related to the parts which are crossed out or marked as N/A in the application notes:
http://www.ti.com/lit/ds/symlink/lm25118.pdf (Page: 29)
http://www.ti.com/lit/ug/snva614b/snva614b.pdf (Page: 11)
One big issue for us was, what does it mean "Do not place"? Open ciruit or shortcut?
Both of course, depending on the removing part.
So we tried different possibilities.
General rule: parallel parts are open; series parts are closed.
We expierienced different behaviours by experiementing different circuits.
On one trial, the buck mode was working. But we forgot the precise combination, unfortunately. ;)
So, finally we took the combination suggested in the user's guide:
http://www.ti.com/lit/ug/snva614b/snva614b.pdf (Page: 8)
- C14; C19; R7; R13 open circuit (DNP... Do not placed?)
- R1 shortcut (equal to 0R)
- D1 replaced with 1N5819 to fit the proposal in the list. (It's not just crossed out. ;) )
Again, the result is:
> Below 10V input voltage it converts it into ~6V and below 10V it shuts down.
Do you have an idea what we did wrong?
If it's helpful, here is our circuit diagram:
https://drive.google.com/folderview?id=0B__8TgcLX5sSTFVIeU00NXU0TVk&usp=sharing
Part mapping:
D1 --> D13
R1 --> R49
R7 --> R48
R13--> not in diagram
C14--> C44
C19--> C42
We would be very thankful for every hint you have for us.
Thank you very much
Fabian
Berlin/Germany
-b option couldn't help.
-a -c -m"..\SAW\Debug\DAWDlRx_3.map" -o"..\SAW\Debug\DAWDlRx_3.out" -w -x -i"..\Ylib" -i"C:\Program Files\C6xCSL\lib_3x" -i"..\ALib" -l"a_dcs_v1.a62" -l"csl6416.lib"
Generally speaking, linking stalls while using 6.1.x and up (e.g. 6.1.x, 7.0.x, 7.1.x, 7.3.x, etc) but works for 6.0.x. 7.3.1 is one of them tried. While 6.1.2 is used, linking stalls with a message: "C:/Program Files (x86)/Texas Instruments/C6000 Code Generation Tools 6.1.2/include/math.h", line 217: remark #681-D: call of function "__isnan" (declared at line 214) cannot be inlined".
[quote user="Dave Nadler"]I'm trying out CCS 6.0.0.00190 with MSP430 GCC Tools 4.8.0.20140423,
and all the latest updates installed as of 11-July.[/quote]The CCS Memory Allocation view appears to parse the output of the "XML link information file" which is generated by the linker of a TI compiler, as specified by --xml_link_info file option.
With CCS 6 projects built using a TI compiler I found that the Memory Allocation view is populated.
However, with CCS 6 projects built using a GCC compiler I saw the same problem as you, in that the Memory Allocation view didn't display the memory usage with a "The project must have its link-info file path set. Click here to initialize the link-info file path..." message. Clicking here didn't have any effect.
Therefore, I think the CCS 6 Memory View isn't supported when a GCC compiler is used - although I can't find any statement to that effect in the CCS 6 help.
Doing a design using a TPS61230
Current limit on this part as a rather complicated affair. The Web bench tool used to calculate and display many parameters seems to omit this key aspect of a power supply design. Did I miss this? Is it there somewhere?
IIRC (from a different thread), the CCS library doesn’t support timezones. Instead, as posted, it uses a different base tiem ('epoch' that corresponds to UTC-6.
So "UTC" and localtime are the same if you life at UTC-6. But if you have a different localtime, things start to get confusing. And of course the linux tiem value differs form the TI one by 6 hrs.
Hi All,
I got CCS from TI seminar and installed in PC, and now as the 90days duration is over, i am unable to work on it.
when i checked in TI, it is mentioned by using XDS100 emulator we can make the expired CCS to work for unlimited time duration. Is it really true & how it is possible to make a high value software tool to run for unlimited duration by using low cost XDS tool?
Kindly need clarification on the above
Regards,
Arvind
Hi Ki,
Renaming ctools.dll into ctools.bak did help. I'm now able to connect to the Cortex A8. Thanks for the support.
What are the side effects of renaming this file? Is this bug already recorded?
Best regards,
Patrick
Hi George,
I have a question about the compilation tool chain of C3x series.
We have two kinds of devices and each of them use different tool chain, one is 4.70 and another is 5.11. What differences are there in the two set of compilation tool chain?
Tool chain v4.70
Tool chain v5.11
I use the different tool chain to compile a same file and I get the different .asm files.
By using v4.70, I get the following assembly code.
****************************************************** * TMS320C30 C COMPILER Version 4.70 ****************************************************** ; C:\tic3x4x\c3x4x\cgtools\bin\ac30.exe -v31 -q -mr -x -dNDEBUG -dNU_NO_ERROR_CHECKING -dCR_INC_STATUS -dCR_INC_RX_MSTAG -i\Tools\ ; C:\tic3x4x\c3x4x\cgtools\bin\opt30.exe -v31 -q -r -a -f -O2 C:\DOCUME~1\micom\LOCALS~1\Temp\security.if C:\DOCUME~1\micom\LOCALS ; C:\tic3x4x\c3x4x\cgtools\bin\cg30.exe -v31 -q -p -a -c -i -a C:\DOCUME~1\micom\LOCALS~1\Temp\security.opt security.asm C:\DOCUME~1\micom\LOCALS~1\Temp\security.tmp .version 31 FP .set AR3 .globl _atof .globl _atoi .globl _atol .globl _strtod .globl _strtol .globl _strtoul .globl _rand .globl _srand .globl _calloc .globl _free .globl _malloc .globl _bmalloc .globl _minit ... BZ L7 NEGI R2,AR2 OR @CONST+7,AR2 CALL _plerr_HandleError ...
By using v5.11, I get the following assembly code.
;****************************************************************************** ;* TMS320C3x/4x ANSI C Code Generator Version 5.11 * ;* Date/Time created: Mon Jul 14 16:25:21 2014 * ;****************************************************************************** .regalias ; enable floating point register aliases fp .set ar3 FP .set ar3 ;****************************************************************************** ;* GLOBAL FILE PARAMETERS * ;* * ;* Silicon Info : C31 Revision PG1-5 * ;* Optimization : Always Choose Smaller Code Size * ;* Memory : Small Memory Model * ;* Float-to-Int : Fast Conversions (round toward -inf) * ;* Multiply : in Software (32 bits) * ;* Memory Info : Unmapped Memory Exists * ;* Repeat Loops : Use RPTB for ALL Loops -- Disallow RPTS * ;* Calls : Normal Library ASM calls * ;* Debug Info : No Debug Info * ;****************************************************************************** ; S:\Tools\texas\ti\c30\bin_511\opt30.exe -v31 -q -r -a -f -O2 C:\Users\SESA15~1\AppData\Local\Temp\security.if C:\Users\SESA15~1\AppData\Local\Temp\security.opt ... cmpi 0,r0 ; |1178| ldine @CL11,ar2 ; |1185| callne _plerr_HandleError ...
Here comes another question, why I use almost the same compilation command to compile the same file by using two compilation tool chain, the result is so different from each other?
You can see from the above example, one is "TMS320C30 C COMPILER" while another is "TMS320C3x/4x ANSI C Code Generator", and one uses CALL instruction and another uses callne instruction.
Hi Jyothi,
[quote user="jyothi sandiri"].and in ccs6 how to define the processor 6713 which i use?[/quote]
See:
http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/353978.aspx
Thanks
ki
Hi
Please populate VCC capacitor and connect VCCX to ground
DNP means 'Do Not Populate'.
Regards,
Amit, it does use RTOS. It's version is tirtos_tivac_2_00_01_23. Here is my project:
(Please visit the site to view this file)
Don
From within CCS, there is also the Scripting Console:
http://processors.wiki.ti.com/index.php/Scripting_Console
ki
Too late for the original poster, but in CCS5
copy the source project (select it and Ctrl+C)
paste it (Ctrl+V)
The Copy Project dialog allows you to rename the copy.
Everything is copied: subfolders, links, includes, processor options, all the details that a manual approach could miss.
Fred,
Unfortunately I don't have the same board as you, but from the screenshots it seems that a GEL file ran to completion and CCS is automatically managing the target configuration. Also, the example project properly assigns code to valid memory addresses on the target (these details are discussed at this wiki page).
Therefore, the only detail I can think may be impacting your debugging experience is the fact the revision of your AM3359 ICE board may be different than the GEL file itself. In practice this translates to the fact the GEL file may not be properly configuring the external memory interface (where the failing 0x80000000 address is).
To check an updated AM3359 ICE GEL file, check the device support page below:
http://processors.wiki.ti.com/index.php/Device_support_files
The GEL files for the ice board are installed at ccsv5/ccs_base/emulation/boards/ice_am3359/gel/
Hope this helps,
Rafael
It is definitely odd that a working environment/setup suddenly started exhibiting this behavior.
Do you have any anti-virus running that could be interfering with the build process? Does the same thing happen when you create a new project in a clean/new workspace and simply try to build a simple project with a basic main.c?
I found this thread that seems to be related and gives some ideas on other things that could possibly cause an interference.
Please attach the full contents of the Console view (not the Problems view) which shows those diagnostics. Please attach the source files referred to, preprocessed like this.
Thanks and regards,
-George
[quote user="Pashan None"]It is really difficult for us to change the compiler at this stage of the development activity.[/quote]
Upgrading your compiler from version 4.9.7 to 4.9.9 is a particularly low risk change. The only difference between these versions is bug fixes, including one bug fix you need. Thus, this particular version change is likely to increase the stability of your builds. Please see this wiki article for more detail.
Presuming you still cannot upgrade ...
I'm a little confused that you now want 4-byte alignment everywhere. Up to this point your focus was on getting only 2-byte alignment, and avoiding holes caused by 4-byte alignment.
Here is a way to force 4-byte alignment between input sections.
.Managed_RAM_Area { . = align(4); file1.obj(.bss) . = align(4); file2.obj(.bss) . = align(4); /* and so on */ } > MANAGED_RAM, type = NOINIT, SIZE(MANAGED_RAM_DATA_LENGTH),
RUN(MANAGED_RAM_START_LOCATION)
Note how I create the symbols for the section size and start address. This avoids some known problems with using the '.' operator to create symbols. And it collects those symbols together in one place.
Instead of ...
[quote user="Pashan None"] . = . + (0xF0 - .); /* Reserve the remaining space */[/quote]
I think you would be happier using the fill=value attribute when you define the MANAGED_RAM memory range in the MEMORY directive.
Thanks and regards,
-George