Andy,
Yes there was a change to the GEL file in CCSv6 that broke the ability to conenct to running targets. Please see this related thread. This should be fixed in CCS 6.0.1, which is due out in the next week or so.
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Forum Post: RE: CCSV6 broke abilitiy to connect to target without reset
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Forum Post: Build version number CCS - Multicore DSP - C6000 series
Hi,
I would like to add a build number into CCS project, where I can always display whenever linker generates final executable, I know version number automatically? Is there a way to get a build number, as well it increments automatically. Pl. advise.
Regards,
Hari
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Forum Post: CCS 5.4 misplacing files during compilation
When I try to compile files with Code Composer 5.4 I am getting the following errors:
Fatal error #5: could not open source file "../interrupt_csl.c"
1 fatal error detected in the compilation of "../interrupt_csl.c".
Compilation terminated.
gmake: *** [interrupt_csl.obj] Error 1
>> Compilation failure
Every time I try to compile, the file interrupt_csl.pp is being created on my desktop when it should it should be saved in "${PROJECT_ROOT}/Debug/Modules". It definitely seems that the linker or compiler is looking for this preprocessing file or for the source code but somehow the directories are being switched around.
This is happening at work with code that is known to work on other machines. The paths are all correct and were double checked in comparison with a working setup. I have checked "Linked Resources" and "Include options" as well as every other item in the Properties explorer and to verify that every single setting is the same as they are on the working setups, so I don't understand why these paths getting all mixed up.
I'll add that this is a new problem. In the past I have been able to compile projects without any problem. It is just this week that all of the sudden I am getting these strange errors. I tried compiling several different projects that have worked in the past, and with all of them I am getting the same errors
Any help would be appreciated. Thanks in advance.
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Forum Post: RE: PSPICE Models run in HSPICE?
Tim,
PSpice models will typically not in HSpice directly as the syntax is not completely compatible. They may require manual syntax conversion.
Best regards
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Forum Post: RE: Why does CCS6 not recognize NULL?
NULL is part of C++, therefore it is a bug in CCS software, can you please submit this bug? I am not allowed to turn off the static code analysis, in fact I have to use the strict ANSI C++03. Let me know when it is resolved.
Than you....
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Forum Post: RE: PSpice model encryption with MicroCap
Nicolas,
The unencrypted model is attached. You could also try using the TINA-TI model. TINA-TI is a free simulator that we provide to our customers.
(Please visit the site to view this file)
Thanks
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Forum Post: RE: SABER simulation models
I could not find either of these parts in TI's portfolio - LM1054 or LM220670.
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Forum Post: RE: Command-line error: invalid option: c++03
Thank you, but actually I do not believe that that option is needed. The strict C++03 is the default option.
Per compiler MSP430 Compiler Users Guide 5.16
ISO C++03 (--c++03, default for C++ files)
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Forum Post: RE: webbench does not allow to force higher frequency on LM3481
Hi Koen,
What input/output conditions are you using? (Vin(min), Vin(max), Iout, Ta)
Thanks,
--Hadi
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Forum Post: RE: Web Bench
Hi Martin,
The DMN6068SE N FET that you proposed can handle current up to 5.6A max. The TPS40210 is a high input/output Boost device that has a max current of 6A. Considering the current derate factor for your FET selection, the DMN6068SE N FET may not tolerate the 6A operation.
Please let me know if you have any question or comment on this.
--Hadi
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Forum Post: RE: Using Webnech Power Designer
Hi Journey,
Can you please provide me some information of your input voltage range?
Thanks,
--Hadi
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Forum Post: RE: How to place a DATA_SECTION at the end of RAM in CCSv6
Thanks AartiG!
I added the following to my linker command file:
SHARED_DATA : {} > SRAM (HIGH)and it worked.
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Forum Post: RE: MSP430 optimization error
I set it by going to properties/
then
c/c++ Build
optimization (maximize window to see selections.)
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Forum Post: RE: how to force double alignment to 4 bytes from gcc for ARM?
Thank you Alberto. Your post was key to my understanding what was going on.
Actually someone suggested __attribute__((packed)) yesterday and it fixed the problem (I was planning on updating the post today anyway), but I didn't understand why there was a discrepancy between what was in memory and what the compiler thought was in memory.
I looked at how the data was getting put into memory, and then the cause was clear. To put the data in memory, I am reading fields from a database one by one, incrementing a pointer to memory by the size of the data type of the field each time. So when I put the data in memory there is no 4 byte gap before the double because I didn't create one.
Rather than trying to guess where the compiler is going to insert gaps and create them when I put the data into memory, it seems like the better solution is to use __attribute__((packed)).
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Forum Post: CCS v6 Breakpoints not reloading after each "Debug( F11)"
I have been seeing flaky behavior from the software breakpoints for a while, but have still had good luck with HW breakpoints, except there aren't enough of those. I guessed that it had something to do with the debugger loosing track of where lines were, when I added a line , or commented a block out, until today....
Today, I noticed that the software BP would stop working every time I reloaded to change only the argument of one assignment line, it was only a one bit change, so it should not affect the instruction ordering. Here is a screen shot, with an 1 error shown when it works only on the HW break point, but not the 3 obviously marked, and enabled, SW breakpoints...it just runs until it gets back to line 205, where the HW breakpoint is. This is how it looks and works just after a Debug/Reload(F11)
Now if I double click each of the SW breakpoint "blue dots" on lines 210,222,234, then everything works , and it stops properly on each breakpoint, but now I get four red errors listed in the console, perhaps one for each break-point? Screenshot below:
And that works until, I Debug/Reload via F11 again, and then it goes back to the behavior in the first screen shot.
Supporting Details:
- CCS v6 Version: 6.0.0.00190
- TMS28069
- Code is in flash but moved to 28069 RAM on boot, thus all breakpoints are in RAM
- Spectrum Digital XDS560V2 Traveler Emulator
- Another problem that I've had since going version 6 is the the Auto Complete, via Ctrl-Space, doesn't seem to work all the time, especially for enumerated types, and register structs. I had to manually look up the exact spelling of SpiaRegs.SPIFFRX.bit.RXFIFORESET yesterday, which was excessively tedious. This may not be related.
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Forum Post: RE: Error in import Eagle script file generated by WEBENCH
Hello Yoong,
I apologize for the late response.
You are right, there are some error messages when you run the script but they can be ignored. Please make sure you ran the library script in the library window. Attached file contains the instructions to import the library file and link the schematic components to the library and generate a board netlist (ratsnest) with footprints.
If you still have issues, share the WEBENCH design with me at howard.chen@ti.com and I can process it for you.
(Please visit the site to view this file)
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Forum Post: How to avoid hole reusing again
Hi,
The following map fill is genrated:
00897940 00000010 ti.csl.ae66 : csl_tsc.oe66 ($Tramp$S$$CSL_tscRead)
00897950 00000010 --HOLE-- [fill = 0]
.switch.2
* 0 00897950 00000010
00897950 00000010 HDL_PDU.obj (.switch:HDL_PushToLmacQue)
Why is the section filled with hole and the address reused by .switch.2?then how to avoid this?
Thanks.
Hengwei
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Forum Post: Memory use display in CCS
I'm trying out CCS 6.0.0.00190 with MSP430 GCC Tools 4.8.0.20140423,
and all the latest updates installed as of 11-July.
As any developer, I need to see current memory use by the project.
I'm expecting to see something like (image from Rowley Crossworks):
Even better would be a summary breakdown segregating RAM use (stack, heap, variables, free)
and flash (libraries, user code, user data).
Unfortunately, all I can find is this:
I click on "here" and nothing happens...
HELP!
Thanks in advance,
Best Regards, Dave
PS: Here's another example from Microchip MPLABX:
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Forum Post: ALIGN 2 doesn't align at HALF WORD Boundary for TI ARM 4.9.7 compiler
Hello Support,
Attached is a ZIP file where you can see that even though ALIGN 2 is present in the .\Debu\tctrmmrc.lst file, the corresponding CONST item is aligned to 4 Byte address in the .\Debug\test.map file.
Once you unzip the contents using WINZIP FOLDER option, you can run compile.bat file in case you want to rebuild yourself. Assuming you have the same path of 4.9.7 TI ARM compiler in your PC.
Else, you can change the path in compile.bat line
set COMPILER_PATH=
Attached is a picture of the MAP file to highlight the problem.
Let me know if you can't see the problem I am talking about.
Any help is appreciated.
Thank you.
Regards
Pashan
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Forum Post: RE: Accessing internal registers and memory in the AM335x
Thanks!
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