Team,
I am using the C6678 Device functional sim (little Endian) from CCSv5.5.
I am able to run the basic EDMA CSL example located at the below wiki post (see 2476.main.txt attachement) on it:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/177116.aspx
Following the CIC0 system event 6 (that correspond to EDMA event) the CPU core 0 receives the interrupt event and runs the ISR accordingly.
Now I want to check that I can manually trigger the same interrupt just by writing to the "System Interrupt Status Raw/Set Registers" (see SPRUGW4A page 16 and 22).
When I write 0x40 (that correspond to the event 6) at 0x02600200 via the debugger I can see that the "System Interrupt Status Enabled/Clear Registers" at 0x02600280 is set accordingly with 0x40 meaning that the event was recognized.
However the Core 0 does not seems to recognize the interrupt as it does not jump to the ISR.
I don't think it is the expected behavior. Could you please confirm? My understanding is that writting to "System Interrupt Status Raw/Set Registers" is equivalent to have a system event generated by the on-chip peripherals.
I unfortunately do not have the EVM to test it on a real silicon.
Thanks and best regards,
Anthony