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Forum Post: CCSv5 multicore debug question

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Hello,

I'm debugging a single-image multicore application on a custom C6678 hardware.
The program gets started with CCS as follows: CCS is only connected to core 0. When loading the program, my .gel script starts the slave cores, which are waiting in the ROM Bootloader (RBL) for the boot magic address. They start an initialization routine which copies all private sections from core 0. Then all cores start the program itself (_c_int00()).

Everything is working fine, but as soon as I establish a connection to a slave core after the program was started, the program counter changes to address 0x20B00000 (RBL) on this core. This only happens if I do a System Reset before loading the program. But I need the System Reset to make sure everything gets initialized properly. It's like CCS remembers the System Reset and executes a core reset after a new connection.

Is there a way to avoid this behavior?

Thanks,
Ralf


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