Hi Harold,
The noise sensitive signals used for control of the IC RT, SS, FB, VDD and TRK should all have their ground return connect to the AGND pin first. Anything in the power path which includes the input capacitors, output capacitors, and low-side FET should use the PGND. The two grounds are kept separate because the power path grounds have the high di/dt signals which can interfere with the control circuitry. They are kept separate by splitting the ground planes horizontally as can be seen on the bottom and top layers of the EVM. The PGND plane connects to the AGND plane underneath the IC. Please see the image below.
Does this help clarify?
Best Regards,
Anthony
