I tried messing with TCLK but no value seemed to change anything. Below are the Test Connection results.
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\NVD\AppData\Local\.TI\1378298878\
0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
The library build date was 'Oct 3 2012'.
The library build time was '22:14:17'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ZERO on its EMU[0] input pin.
The controller has a logic ZERO on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: B:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 none - 07 13 10.13kHz - similar isit internal clock
2 none - 07 1E 11.47kHz {-} similar isit internal clock
3 512 - 07 13 10.13kHz O good value measure path length
4 512 - 07 13 10.13kHz {O} good value apply explicit tclk
The first internal/external clock test resuts are:
The expect frequency was 10131Hz.
The actual frequency was 10131Hz.
The delta frequency was 0Hz.
The second internal/external clock test resuts are:
The expect frequency was 11474Hz.
The actual frequency was 11473Hz.
The delta frequency was 1Hz.
In the scan-path tests:
The test length was 16384 bits.
The JTAG IR length was 4 bits.
The JTAG DR length was 1 bits.
The IR/DR scan-path tests used 4 frequencies.
The IR/DR scan-path tests used 10.13kHz as the initial frequency.
The IR/DR scan-path tests used 11.47kHz as the highest frequency.
The IR/DR scan-path tests used 10.13kHz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
The frequency of the JTAG TCLKR input is measured as 10.13kHz.
The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
The target system likely uses the TCLKO output from the emulator PLL.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 4 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]