CCS 5.3.0.00090 is showing me the following diassembly for a LM4F120H5QR target:
[quote] sqrtf:
00004928: EEB50AC0 FCMPEZS S0, S0
0000492c: B508 PUSH {R3, LR}
0000492e: EEF1FA10 FMXR PC, FPSCR
00004932: D206 BCS $C$L1
00004934: 2001 MOV R0, #0x1
00004936: F7FFFE2F BL _Feraise
0000493a: 4803 LDR R0, $C$CON1
0000493c: ED900A00 FLDS S0, [R0, #0]
00004940: BD08 POP {R3, PC}
$C$L1:
00004942: EEB10AC0 FSQRTS S0, S0
00004946: BD08 POP {R3, PC}[/quote]For the first instruction EEB50AC0 according to the ARM®v7-M Architecture Reference Manual I would have expected the disassembled instruction to be:
[quote]FCMPEZS S0, 0.0[/quote]Rather than the following which is disassembled by CCS 5.3:[quote]FCMPEZS S0, S0[/quote]Based upon the source code for the sqrtf function from the TI ARM compiler 5.0.5 RTS I expect the first instruction to a comparing S0 against zero, rather than what the CCS diassembly is showing as a compare of S0 against S0.
Under the CCS Project Properties -> Debug -> Cortex M3 Disassembly Style the default of "Mixed ARM/Thumb" is selected.
On a related note, is it possible to get the CCS ARM diassembly to list the Unified Assembler Language (UAL) mnemonics, rather than the "legacy" mnemonics?