Hi AartiG,
That means ADC (Register plots) for other TI processors are simulating FIFO status flags correctly during an XDS100v2 debug simulation when one of any number of sequencer is configured TRIGGER_PROCESSOR?
That SS0-3 trigger was also and originally configured to post an interrupt, sequence complete for what ever reason. I had to use another sequencer first 2 than 1 because there was some kind of hardware issue and documented errata with sequencer 3. In that with you I agree there might be a monkey inside the die looking for a banana.
Find it difficult to point a finger at the Stellaris group when the debug simulation is not correctly processing the data received from the XDS100 emulator even with a reduced JTAG speed setting. The steps needed to reproduce this issue were posted in the Stellaris link. Two CCS5 screen shots showing the debug behavior in the yellow high lighted bars being asserted for the wrong register SS0-0 when SS0-1 was asserting code. The absence of any FIFO full or empty flag change was typical for sequencers 1-3. Source stepping code that should assert sequencer 1 was actually asserting sequencer 0 register status changes. The SS0-1 FIFO empty & full flag being (if) tested remained always as (empty 1) for any tested sequencers 1-3 even for a sequence ((full) guessing) but the source stepping would conditionally branch as if the flag was true. Sequencer 0 was toggling both empty & full flags upon source stepping code for SS0-1. Sequencer 0 was configured trigger an hardware interrupt when PWM0 counters reach zero and all the PWM generators Debug switch are set to Run when JTAG connected. That PWM0 interrupt would explain some of the random yellow highlight but not all, especially when source stepping code not related to unrelated ADC registers.
http://e2e.ti.com/support/microcontrollers/stellaris_arm/f/471/p/327865/1142783.aspx#1142783