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Forum Post: RE: Memory access problems using XDS100v2

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If you haven't figured it out already, the boot mode on the LCDK board is controlled by SW1 DIP switch. The switch bits SW1[4:1] are inverted levels of BOOT[4:1]. Physically, the switch is oriented from left to right as LSb to MSb to make it more confusing.
SW1[0:7] SW1[7:0] BOOT[7:0]
01010000 00001010 00010100 UART
01110000 00001110 00010000 NAND
00000000 00000000 00011110 Emulation Debug
The UART and NAND settings are in the LCDK board doc. The other modes you have to string together from info in the schematic and the processor manual.

EDIT:
Oops. Misread my notes. The board is wired to swap ends. Not the switch SW1[1]=BOOT[4], SW1[2]=BOOT[3], SW1[3]=BOOT[2], SW1[4]=BOOT[3].
SW1[8:1] BOOT[7:0]
00000101 00010100 UART
00000111 00010000 NAND
00000000 00011110 Emulation Debug

Anyhow, set SW1 to all 0 for emulation debug. Just remember what it was before you changed it.

EDIT:
Oops again. One last try.
SW1[8:1] BOOT[7:0]
00001010 00010100 UART
00001110 00010000 NAND
00000000 00011110 Emulation Debug


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